Quiet Charge

A circuit is a loop. Charge can only do useful work if it has a way out as well as a way in. A battery (or a power supply) holds one end of the loop at a higher electrical potential than the other. A wire and a load — a lamp, a motor, a tiny capacitor inside a chip — close the path. Nothing has to be visible. The same pattern, shrunk a million times, is what a processor is made of.

Three words do almost all the work. It helps to meet them as everyday quantities before they turn into symbols.

A useful way to remember the three working variables: voltage is how hard each bit of charge is being pushed, current is how many bits of charge are on the move, and power is those two multiplied — push times traffic. A high-voltage, tiny-current circuit and a low-voltage, huge-current circuit can deliver the same watts. USB power banks and laptop chargers play this game in reverse: they raise current so they can keep voltage modest.

People often borrow a water picture, and it is a good first map if you keep one caveat in mind. Voltage is the pressure difference, or the height of a tank. Current is the flow rate through the pipe. Resistance is how narrow the pipe is. Power is how much work that flow can do, or how warm the pipe gets. Charge is the water itself. Capacitance is the size of the tank.

The caveat is the important one for computers. The pipes are already full. Copper is packed with mobile charge before you close the switch. Turning a circuit on does not wait for “electricity” to travel from the battery to the chip, the way an empty hose waits for water. What travels quickly is a pressure change — in electrical language, an electromagnetic field — that slightly rearranges the charge that was already there. Individual electrons drift slowly; the message does not. In the picture below, the dots jiggle in place. The pale band is the bit.

Two more words that will keep returning, defined here so they never ambush you.

Decade. In ordinary English a decade is ten years. In electronics a decade is a factor of ten in whatever you are measuring. “Sixty millivolts per decade” means: change the voltage by 60 mV, and the current changes tenfold. Six decades of on/off is a factor of a million between the on-current and the off-current. Whenever this lecture says decade, it means that factor of ten.

Ground, and Vdd. Ground is the voltage we choose to call zero, the return path of the loop. Vdd is the positive supply of a CMOS chip — complementary metal–oxide–semiconductor, the style of almost every modern processor; historically “drain voltage,” now just “the rail.” A digital 1 is a node sitting near Vdd; a digital 0 is a node sitting near ground. Everything else in the lecture is a refinement of that sentence.

An electron is a tiny packet of negative charge. The packet's size is fixed by nature: e = 1.602×10⁻¹⁹ coulombs. A coulomb is simply a large number of those packets — about 6.24×10¹⁸ electrons. One ampere is one coulomb per second through a cross-section, so a 1 A charger is a conveyor of six billion billion electrons every second.

That sounds like a rush. Inside a metal it is almost the opposite of a rush. Copper already holds about 8.5×10²⁸ conduction electrons per cubic metre, a Fermi sea that is almost full. They are not waiting at the battery to be sent down the wire. They are already everywhere in the wire, jiggling at around a million metres per second.

Current is a slight bias on that jiggle. Push a coulomb of extra charge in at one end and a coulomb leaves the other end almost immediately — but those are not the same electrons. The ones that left were already sitting at the far end. What travelled fast was the electromagnetic field that told every electron, all along the wire, to lean a little the same way.

Voltage is not a substance and it is not “strength of electricity.” It is a difference in potential energy, quoted per unit charge. One volt means one joule of energy for each coulomb that falls through the difference — or, for a single electron, one electron-volt: 1.6×10⁻¹⁹ J.

In a battery the difference is chemical. In a laptop charger it is an electromagnetic field maintained by a switching converter. In a MOSFET — a metal–oxide–semiconductor field-effect transistor, the switch a chip is made of — it is the height of an energy hill the electron has to climb to enter the channel. Same units, same meaning: how much energy you give, or take, per charge.

Two pictures of the same 0.8 V, 0.2 A circuit: 1.25×10¹⁸ electrons per second, each giving up 0.8 eV. Or: 0.16 J every second. The electron picture is useful when you want to know how many carriers a node holds. The joule picture is useful when you want to size a heatsink.

In vacuum an electron really would fall through a volt and pick up 1 eV of kinetic energy. In copper it collides with the lattice about every femtosecond. The energy that might have become speed becomes phonons — vibrations of the metal, which we feel as heat — almost immediately. That is resistivity. Drift is the small leftover after a very busy thermal life.

A digital bit on a circuit board is not a boxcar of electrons. It is a brief step in the voltage between a signal conductor and its return path. The step is an electromagnetic mode riding in the insulator around the wire, typically around c/2 — half the speed of light. At the receiver, that mode slightly rearranges the Fermi sea on a transistor gate, which is a capacitor of a few femtofarads. A few thousand extra electrons on that gate are enough to flip the next inverter.

CMOS logic — complementary metal–oxide–semiconductor, the style of almost every modern chip — draws almost no current in a quiet state. A “1” is a capacitor charged to Vdd. A “0” is the same capacitor emptied to ground. To switch, you open a MOSFET and let charge flow onto or off of that node. The MOSFET is a voltage-controlled hill: the gate voltage lowers a barrier so electrons from the source can enter the channel.

The hill itself is thermal. Electrons in the source have a Boltzmann tail of energies. A barrier of height qV — charge times voltage — leaks a current proportional to e^−qV/kT. At room temperature that exponential is a decade of current for every 60 mV of barrier (the ideal subthreshold swing). A decade, as in the primer, is a factor of ten, not ten years. To be firmly off you want several decades, which is several factors of ten. That is why a 2026 CPU still likes around 0.7 V, rather than 70 mV.

A 3 nm-class CPU core sits near 0.7–0.85 V when it is working, sometimes down in the 0.5s when it is sipping, sometimes over a volt on a turbo rail. The junction — the silicon itself, under the heat spreader — is often 70–95 °C, which is 343–368 K. This lecture defaults the lab to 358 K for that reason: the physics the transistor sees is a little warmer than the room you are sitting in, and that extra warmth is useful headroom we can still give back.

Memory is a little more conservative. DDR5 DIMMs (dual in-line memory modules) run the array at 1.1 V. HBM3E — high-bandwidth memory — is 1.1 V; HBM4 lowers the core to about 1.05 V. LPDDR5, the low-power cousin in phones and laptops, can run the I/O at 0.5 V, which leaves a smaller swing for multilevel signalling, as we will see. GDDR7, the high-speed graphics sibling, is around 1.2 V and is the one that went ternary.

A few of those labels, in plain language. FO4 is a fan-out-of-4 inverter, a standard yardstick for the energy of one logic gate. SRAM is static RAM, the on-chip cache; DRAM is dynamic RAM, the dense off-chip memory. A PHY is the physical-layer transceiver that drives the pins. NRZ is non-return-to-zero — ordinary two-level 0/1 signalling. PAM is pulse-amplitude modulation, several voltages on one wire (coming in chapter 09). An ALU is the arithmetic logic unit. The pattern in the table is friendly: arithmetic, once the data is sitting next to the ALU, is already down in the hundred-attojoule to femtojoule range. Fetching the data is picojoules. A DRAM access is about a thousand times a DRAM cell store, because you drive wordlines, bitlines, sense amplifiers, and a PHY. Most of the energy in computing goes to moving data, not to the arithmetic itself — which is also the largest opening for improvement.

At any temperature above absolute zero, charge on a conductor is in motion. That motion has a measurable voltage. Johnson and Nyquist wrote it down in 1928: a resistor R in a bandwidth Δf produces a mean-square voltage 4 kT R Δf. On a capacitor the same physics is tidier. Equipartition gives the capacitor ½ kT of energy, so ½ C σ² = ½ kT, and the rms noise — root-mean-square, a typical size — is √(kT/C).

“Several” is a precise number. A Gaussian tail beyond 7 σ happens about once in 10¹² trials; beyond 8 σ, once in 10¹⁵. Serial links quote 10⁻¹² to 10⁻¹⁵ bit error rates (BER) before forward error correction. DRAM and logic also live with coupling from the next wire, supply bounce, and manufacturing variation, so they run with wider margins than pure kT/C would ask for. Thermal noise is the part that is always there. At 0.8 V it is rarely the one you are hitting. Lower the swing far enough, and it becomes the one that matters — which is exactly the experiment the lab is for.

Two details, so the picture is complete. First, kT/C falls only as √T. Halving absolute temperature does not halve the required swing; it takes it down by √2. Second, the MOSFET’s 60 mV/decade does scale as T. For logic voltage, cooling is linear and therefore a larger lever than it is for a capacitor’s Johnson noise. A cold analogue front-end and a cold CPU benefit from cooling in different ways.

Suppose you actually did it. You take a rack, sink the silicon in liquid nitrogen, and redesign the chip so the rails follow the new 15 mV/decade swing instead of 80. Thresholds fall. Overdrive falls. Vdd might be 0.2 V instead of 0.75 V. Switching energy, which goes as V², drops by an order of magnitude. Leakage, exponential in qVth/kT, becomes very small.

Cooling uses power at the wall plug. A refrigerator moves heat from 77 K to 300 K with a well-defined minimum cost. Carnot says the least you can pay is (Th − Tc)/Tc watts of work per watt of heat — about 2.9 W per watt at 77 K. Practical Stirling and Gifford–McMahon coolers typically reach 10–20% of that Carnot factor, so 15–30 W at the wall per watt in the bath. At 4 K the Carnot factor is already about 75, and practical 4 K coolers reach about 1–3% of Carnot, so wall power is hundreds of watts per watt of heat. Liquid helium is how you run a dilution refrigerator for a quantum processor — a specialised, and already working, plant.

The work is painstaking, and teams still do it when the requirements ask for it. Cryo-CMOS at about 4 K is how you sit a control ASIC next to a quantum processor without a thousand coaxial cables. Superconducting RSFQ (rapid single-flux quantum) and AQFP (adiabatic quantum-flux parametron) logic at 4 K switch with about 10⁻¹⁹ to 10⁻²¹ J, which is the closest classical electronics has come to Landauer. IBM, Google, and several startups have published the circuits. Scaling that idea to a training cluster is an engineering question of cooler size as much as of transistors — nitrogen remains the more practical window for bulk classical silicon, and helium the natural home for quantum control.

A near-term step that is already in reach: run the junction closer to 50 °C than 95 °C with liquid in the cold plate. Johnson noise barely notices a few tens of kelvin, but leakage and reliability do, and the 60 mV/decade is a few millivolts kinder. The lab’s “Junction” versus “Room” presets are that story — a quiet, useful opening rather than a leap.

It is worth explaining how many voltages a wire can usefully mean. Binary is only the starting point; the same copper can carry three or four distinct levels, and that choice is how cables and graphics memory bought more bits without buying more pins.

Put three voltages on a wire (−V, 0, +V) and each symbol can carry log₂ 3 ≈ 1.58 bits. Four voltages, 2 bits. Eight, 3 bits. This is pulse amplitude modulation, PAM-M, one of the oldest ideas in communication. Memory and high-speed serial links adopted it once pin rates made analogue bandwidth the scarce resource.

Walk the energy argument slowly. Suppose the only noise is kT/C on a capacitor, and you hold a fixed error rate. Then the spacing ΔV is set by σ, and the total swing must grow as (M−1). Energy stored goes as V², so as (M−1)². You get log₂ M bits. Energy per bit goes as (M−1)² / log₂ M, which is a minimum at M = 2 and then rises. On a quiet capacitive wire, binary is the thermodynamic optimum of this family.

That is a different channel from the one GDDR or PCIe lives on. A PCB (printed circuit board) trace, a package via, a long copper pair — those are low-pass filters. Loss in dB grows with frequency, often roughly linearly in GHz for the lengths we care about. At 32 Gb/s, NRZ has its Nyquist at 16 GHz; PAM-3 at the same bit rate sits at 10.1 GHz; PAM-4 at 8 GHz. If the trace costs you a decibel per gigahertz, PAM-3 just received a 6 dB gift, which exactly balances its 6 dB cost, and PAM-4 received 8 dB against a 9.5 dB cost. Nudge the loss or the rate and the winner flips. There is a best M for each channel, and finding it is the fun of the job.

It is worth pausing on this, because the two memories are easy to mix up and the physics is genuinely interesting. The memory that ships ternary today is GDDR7. HBM3E and HBM4 still send ordinary two-level NRZ. They send it on 1024 or 2048 wires at once, through a silicon interposer, at 1.05–1.1 V. GDDR7 sends PAM-3 (−1, 0, +1) down a much narrower bus on a graphics board, at pin rates of 28–40 Gb/s. Same family of electrons. Opposite packaging physics — and both answers are the right one for their channel.

HBM’s channel is short, dense, and gentle. A silicon interposer millimetres long does not attenuate 16 GHz the way a six-inch PCB does. The scarce resource is edge bandwidth density — terabits per second per millimetre of shoreline — and the way you buy that is more pins, not more bits per pin. Extra voltage levels would add comparators, linearity work, and crosstalk in a bundle of a thousand neighbours, for a Nyquist gift the interposer does not need. Research papers have built PAM-3 PHYs aimed at future HBM-class densities. The shipping stacks have stayed with two levels, which is the optimum of Regime A talking.

GDDR is Regime B. You get 32 or 128 pins, not 1024, and they run across a board. GDDR6X tried PAM-4 and it worked, with extra analogue care: three eyes, tight linearity, more comparators. GDDR7 stepped to PAM-3. Three levels, two eyes, 1.5 bits per UI (3 bits in 2 UI with 11b/7s and 3b/2s coding, actually about 1.57). SNR cost of 6 dB instead of 9.5. Two comparators instead of three. JEDEC’s first standardised PAM DRAM. USB4 Version 2.0 made the same call for the same reason.

LPDDR, the phone and laptop cousin, is a useful comparison. LPDDR5’s I/O is 0.5 V. A 0.25 V swing split into three or four levels leaves a slim margin after noise, simultaneous switching, and a compact package. Papers say so directly: the swing is what keeps PAM out of LPDDR. Low voltage and multilevel signalling pull in different directions unless the channel is quiet enough to afford the split. HBM is quiet and still stays binary because width is the cheaper way to buy bandwidth. LPDDR is neither as quiet nor as wide, so it stays binary and takes the pin rate that two levels can support.

DDR5, on a DIMM with stubs and connectors, is also still NRZ, at 1.1 V, with decision-feedback equalizers and a lot of training. The DIMM channel has many reflections; extra levels would copy those reflections into extra eyes. Two levels remain the better match for that particular shape of channel — another case of the physics pointing at a clean answer.

In 1961 Rolf Landauer observed that erasing a bit is not only a bookkeeping operation. It is a compression of the machine’s physical state space, and it has a minimum heat: kT ln 2 per irreversible erasure. At 300 K that is 2.87×10⁻²¹ J, about 2.9 zJ. At 358 K, a little more. At 4 K, 38 yoctojoules. That floor is a destination.

A modern FO4 inverter at 3 nm is a few hundred attojoules — already only about 10⁵ Landauer bits, closer than a casual comparison of joules sometimes suggests. The inverter is doing well. The larger remaining cost is the millimetre of copper to the next inverter, the millimetre of interposer to HBM, the centimetres to a DIMM. Communication, not NAND, is where most of the joules still go — and where the next gains are waiting.

Even the DRAM cell, a textbook capacitor, sits above Landauer. A 2025 experiment that counted electrons on a real DRAM cell found the measured heat stayed above the line: the cell is not prepared in thermal equilibrium the way the derivation assumes, so the erasure is not quasistatic. CMOS structure itself is part of the thermodynamics. Reaching the floor is a device-design project as much as a supply-voltage project — which is an invitation.

Let us stay with classical physics — electrons, fields, maybe Cooper pairs, no qubits — and ask a hopeful question. What is the most signal those electrons can carry, the most compute they can do, the least power they may use — and which parts of that design point toward materials still being grown in the lab?

Information, classically, is distinguishable states. N independent two-level systems hold N bits. An electron in a box is not quite that: it occupies modes of a Fermi sea, and distinguishability is set by thermal smearing ~kT around the Fermi energy and by shot noise when you try to count. A current pulse of N electrons can encode, by amplitude alone, roughly ½ log₂ N bits before Poisson noise blurs the levels. Timing, phase, and spatial modes add more, up to the Shannon capacity of the physical channel.

The machine at the limit, drawn as an engineering spec:

• Keep data close. The cheapest bit is the one that was already at the ALU. In-memory and near-memory compute are how you approach the floor, because a millimetre of copper is already 10⁵ Landauer bits.
• Erase as little as possible. Reversible pipelines (Bennett, adiabatic CMOS, Bennett clocking) pay Landauer only on the bits you truly let go — I/O, measurement, architectural commits.
• Encode at the channel’s Shannon rate. On short quiet wires that means binary at the smallest reliable V. On long lossy wires it means the PAM-M (or a shaped constellation) that maximises bits per joule after the low-pass. Uniform PAM leaves a 1.53 dB shaping gap to a Gaussian constellation; at the limit you take that too.
• Pick T with Carnot in mind. Logic voltage can fall with T; Johnson noise falls only as √T; cooler watts grow as 1/T. A redesigned CMOS part at about 77 K is the interesting classical compromise. 4 K is a natural home for superconductors.
• Change the carrier when charge is no longer the best handle. A single-electron box with C ≈ 1 aF has charging energy e²/2C ≈ 80 meV, above room-temperature kT, so in principle one electron is a bit. Reading it quickly, and wiring many of them, is still research. Superconducting flux quanta Φ₀ = h/2e are the encoding that already works at 4 K (RSFQ, AQFP). Spins and photons are the other classical-ish handles.

Where today’s materials would need to grow to match that drawing:

• Silicon’s bandgap is 1.1 eV — a gift at 300 K, and a starting point for new operating points. Using it at 10 mV rails asks the transistor for a steeper on/off than 0.7 V CMOS provides; tunnel FETs and other steep-slope devices are an active research path.
• Copper resistivity and electromigration set how skinny a wire can be before resistive heating grows quickly. Cobalt, ruthenium, and graphene interconnects are already chipping away at this. Room-temperature superconductors remain a research goal, and a welcome one.
• Gate oxides still need enough field to invert a channel while tunnelling stays in budget. A 10× lower Vdd asks for a different stack, and that stack is being explored.
• DRAM’s trench capacitor and its refresh sit above Landauer, as the 2025 single-electron experiment showed. A Landauer-class memory is a different device — perhaps magnetic, perhaps superconducting, perhaps one still being imagined — and several of those are already in the literature.
• Reversible logic at speed, in a real instruction set, with real I/O, is still an open engineering project. Turning the textbooks into a compiler and a chip is inviting work.

You can take the lab with you. Temperature is a design knob, and a friendly one. Every millivolt on a 5 nm rail, every extra PAM level on a memory bus, every kelvin you return to a junction — from a working 85 °C die toward a cooler plate — is the same argument: a bit must keep its head above water. Heat is that water: a thermal sea whose height we can measure, and whose height we can lower. We already swim with a comfortable margin. The remaining work is to find out how close we can sit to the surface while still reading every bit — and which parts of that closeness are physics, and which are simply how we have usually wired the board. Both are things we can change.